Carry out performance & power architecture exploration through detailed modeling and analysis of one or more of the following functions/components: custom compute components, shared interconnect in a heterogeneous SoC, shared cache/memory subsystem in a heterogeneous SoC, traditional DRAM controllers and 3D stacked memory, Explore various architectures that are targeted towards reducing memory BW and/or memory capacity, Create simulation infrastructure that will support exploring various memory hierarchies, QoS, latency and throughput analysis for heterogeneous platforms consisting of multiple agents with competing resource requirements.