You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Must be pursuing bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or in any STEM related field of study with 1+ years of experience in Design Verification Developing UVM and/or Formal-based verification architectures and methodologies. 6+ months of knowledge or experience in Hardware Design Language (such as VHDL or Verilog). 6+ months of knowledge or experience in C/C++ programming Experience with scripting languages Low power experience (e.g., UPF) Formal verification experience and debugging.