Within the Metrology cluster of ASML, Leveling is the department responsible for capturing the wafer height in a map. Part of this capturing process is to perform wafer map modeling. This modeling is already on the edge on the timing budgets available. To speed-up the calculation in the scanner, leveraging use of state of the art image-processing should be investigated. New ASML scanners already include GPUs (Graphics Processing Unit), so they should be the first candidates for PoC (Proof of Concept) qualifications. The aim of this internship is to investigate, design and ideally start implementing. This assignment is important and will have a significant business pay off, also in the long term. You will be part of a very motivated and helpful Leveling team and report directly to the assigned mentor.