Principal Physical Design Engineer (d/m/f)
Valencia, Spain, Europe

Responsible for PR of digital/mixed-signal devices with Cadence flow and tools, Execute of DfT strategy including pattern generation simulation and scan insertion, Floorplanning of IC’s including integration of memory or any other kind of IP blocks, power grid generation, clock insertion, Responsible for providing clean digital layout from RTL to GDSII (fulfill timing, EMIR analysis), Close collaboration with analog design, layout engineers and digital front-end engineers in the top level (either digital or M/S on top) layout.