The Leveling department has a MATLAB-based simulation framework that enables the simulation of realistic wafers. The simulation framework uses an internal grid to represent the wafer topography and calculate the level sensor measurements. However, due to memory and/or calculation time limitations, the spacing of the grid points might be bigger than the smallest feature on the wafer, leading to aliasing artefacts. Your assignment is to create a better approach for the internal grid, which does not lead to aliasing artefacts and still fits within memory and calculation time requirements. The assignment also includes translating the solution approach into a design and implementing it in the simulation framework, as well as quantifying the performance based on relevant use cases.